TY - CONF T1 - Real Time Head Detection for Embedded Vision Modules T2 - 2007 IEEE International Symposium on Intelligent Signal Processing2007 IEEE International Symposium on Intelligent Signal Processing Y1 - 2007 A1 - Alfredo Gardel A1 - Ignacio Bravo A1 - Pedro Jimenez A1 - Jose L. Lazaro A1 - Torquemada, Antonio AB -

This paper shows the algorithm implementation for a FPGA based design for people counting using a low level head detection method. Different annular patterns are used to process in parallel the image and detect heads of different sizes. Preprocessing and edge extraction are also made using reconfigurable hardware. The developed system exploits hardware processing as the vision algorithm has been modified and tuned for hardware implementation using almost the 100% of area resources of a Spartan3 (1.5 Mgates) and performing in real time with similar results than other more sophisticated algorithms while using very low cost circuits.

JF - 2007 IEEE International Symposium on Intelligent Signal Processing2007 IEEE International Symposium on Intelligent Signal Processing PB - IEEE CY - Alcala de Henares, Spain SN - 978-1-4244-0829-0 UR - http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4447515 ER -