<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="6.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">R. Nieto</style></author><author><style face="normal" font="default" size="100%">R. Mateo</style></author><author><style face="normal" font="default" size="100%">A. Hernandez</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Heterogeneous SoC Architecture for a FBMC Receiver with Channel Estimator and Channel Equalizer in PLC.</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE International Symposium on Power Line Communications and its Applications (ISPLC 2020).</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2020</style></year><pub-dates><date><style  face="normal" font="default" size="100%">05/2020</style></date></pub-dates></dates><publisher><style face="normal" font="default" size="100%">IEEE</style></publisher><pages><style face="normal" font="default" size="100%">1-6</style></pages><language><style face="normal" font="default" size="100%">English</style></language></record></records></xml>